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1. general description the ADC1415S is a single channel 14-bit a nalog-to-digital converte r (adc) optimized for high dynamic performances and low power consumption at sample rates up to 125 msps. pipelined architecture and output error correction ensure the ADC1415S is accurate enough to guarantee zero missing codes over t he entire operating range. supplied from a single 3 v source, it can handle output logic levels from 1.8 v to 3.3 v in cmos mode, thanks to a separate digital output supply. the ADC1415S supports the low voltage differential signalling (lvds) double data rate (ddr) output standard. an integrated serial peripheral interface (spi) allows the user to easily configure the adc. the device also includes a spi programmable full-scale to allow flexible input voltage range from 1 v to 2 v (peak-to-peak). with excellent dynamic performance from the baseband to input frequencies of 170 mhz or more, the ADC1415S is ideal for use in communications, imaging and medical applic ations - especially in high intermediate frequency (if) applications thanks to the integrated input buffer. the input buffer ensures that the input impedance remains constant a nd low and the performance consistent over a wide frequency range. 2. features and benefits ADC1415S series single 14-bit adc; 65 msps, 80 msps, 105 msps or 125 msps with input buffer; cmos or lvds ddr digital outputs rev. 03 ? 12 april 2010 preliminary data sheet ? snr, 72 dbfs / sfdr, 86 dbc ? input bandwidth, 600 mhz ? sample rate up to 125 msps ? power dissipation, 635 mw at 80 msps, including analog input buffer ? 14-bit pipelined adc core ? spi ? clock input divider by 2 for less jitter contribution ? duty cycle stabilizer ? integrated input buffer ? fast out of range (otr) detection ? flexible input voltage range: 1 v (p-p) to 2 v (p-p) ? inl 1.5 lsb, dnl 0.5 lsb ? cmos or lvds ddr digital outputs ? offset binary, two?s complement, gray code ? pin compatible with the adc1215s series, adc1015s series and the adc1115s125 ? power-down and sleep modes ? hvqfn40 package
ADC1415S_ser_3 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. preliminary data sheet rev. 03 ? 12 april 2010 2 of 39 nxp semiconductors ADC1415S series ADC1415S series; input buffer; cmos or lvds ddr digital outputs 3. applications 4. ordering information ? wireless and wired broadband communications ? spectral analysis ? portable instrumentation ? ultrasound equipment ? imaging systems ? software defined radio ? digital predistortion loop, power amplifier linearization table 1. ordering information type number f s (msps) package name description version ADC1415S125hn/c1 125 hvqfn40 plastic thermal e nhanced very thin quad flat package; no leads; 40 terminals; body 6 6 0.85 mm sot618-6 ADC1415S105hn/c1 105 hvqfn40 plastic thermal e nhanced very thin quad flat package; no leads; 40 terminals; body 6 6 0.85 mm sot618-6 ADC1415S080hn/c1 80 hvqfn40 plastic thermal e nhanced very thin quad flat package; no leads; 40 terminals; body 6 6 0.85 mm sot618-6 ADC1415S065hn/c1 65 hvqfn40 plastic thermal e nhanced very thin quad flat package; no leads; 40 terminals; body 6 6 0.85 mm sot618-6
ADC1415S_ser_3 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. preliminary data sheet rev. 03 ? 12 april 2010 3 of 39 nxp semiconductors ADC1415S series ADC1415S series; input buffer; cmos or lvds ddr digital outputs 5. block diagram fig 1. block diagram ADC1415S spi output drivers output drivers system reference and power management error correction and digital processing adc core 14-bit pipelined s/h input stage inp otr sdio/ods sclk/dfs pwd reft cmos: d13 to d0 or lvds/ddr: d13p, d13m to d0p, d0m inm clock input stage and duty cycle control refb clkm clkp sense vref vcm 005aaa10 1 cs oe input buffer cmos: dav or lvds/ddr: davp davm
ADC1415S_ser_3 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. preliminary data sheet rev. 03 ? 12 april 2010 4 of 39 nxp semiconductors ADC1415S series ADC1415S series; input buffer; cmos or lvds ddr digital outputs 6. pinning information 6.1 pinning 6.2 pin description fig 2. pin configuration with cmos digital outputs selected fig 3. pin configuration with lvds/ddr digital outputs selected 005aaa10 2 ADC1415S hvqfn40 d9 agnd vdda3v d8 inp d7 inm d6 agnd d5 vdda5v d4 vcm d3 agnd d2 reft d1 refb d0 vdda3v clkp clkm dec pwd d13 d12 d11 d10 vref sense sdio/ods sclk/dfs otr ognd vddo n.c. dav 10 21 9 22 8 23 7 24 6 25 5 26 4 27 3 28 2 29 1 30 11 12 13 14 15 16 17 18 19 20 40 39 38 37 36 35 34 33 32 31 terminal 1 index area transparent top view cs oe adc1215s hvqfn40 d8_d9_m d8_d9_p d6_d7_m d6_d7_p d4_d5_m d4_d5_p d2_d3_m d2_d3_p d0_d1_m d0_d1_p vdda3v inp inm agnd vdda5v vcm agnd reft refb vdda3v clkp clkm dec pwd d12_d13_m d12_d13_p d10_d11_m d10_d11_p vref sense sdio/ods sclk/dfs otr ognd vddo n.c. dav 10 21 9 22 8 23 7 24 6 25 5 26 4 27 3 28 2 29 1 30 11 12 13 14 15 16 17 18 19 20 40 39 38 37 36 35 34 33 32 31 agnd terminal 1 index area transparent top view 005aaa103 oe cs table 2. pin description (cmos digital outputs) symbol pin type [1] description refb 1 o bottom reference reft 2 o top reference agnd 3 g analog ground vcm 4 o common-mode output voltage vdda5v 5 p 5 v analog power supply agnd 6 g analog ground inm 7 i complementary analog input inp 8 i analog input agnd 9 g analog ground vdda3v 10 p 3 v analog power supply vdda3v 11 p 3 v analog power supply clkp 12 i clock input clkm 13 i complementary clock input dec 14 o regulator decoupling node oe 15 i output enable, active low pwd 16 i power down, active high
ADC1415S_ser_3 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. preliminary data sheet rev. 03 ? 12 april 2010 5 of 39 nxp semiconductors ADC1415S series ADC1415S series; input buffer; cmos or lvds ddr digital outputs [1] p: power supply; g: ground; i: input; o: output; i/o: input/output. d13 17 o data output bit 13 (msb) d12 18 o data output bit 12 d11 19 o data output bit 11 d10 20 o data output bit10 d9 21 o data output bit 9 d8 22 o data output bit 8 d7 23 o data output bit 7 d6 24 o data output bit 6 d5 25 o data output bit 5 d4 26 o data output bit 4 d3 27 o data output bit 3 d2 28 o data output bit 2 d1 29 o data output bit 1 d0 30 o data output bit 0 (lsb) dav 31 o data valid output clock n.c. 32 - not connected vddo 33 p output power supply ognd 34 g output ground otr 35 o out of range sclk/dfs 36 i spi clock / data format select sdio/ods 37 i/o spi data io / output data standard cs 38 i spi chip select sense 39 i reference programming pin vref 40 i/o voltage reference input/output table 3. pin description (lvds/ddr) digital outputs) symbol pin [1] type [2] description d12_d13_m 17 o differential output data d12 and d13 multiplexed, complement d12_d13_p 18 o differential output data d12 and d13 multiplexed, true d10_d11_m 19 o differential output data d10 and d11 multiplexed, complement d10_d11_p 20 o differential output data d10 and d11 multiplexed, true d8_d9_m 21 o differential output data d8 and d9 multiplexed, complement d8_d9_p 22 o differential output data d8 and d9 multiplexed, true d6_d7_m 23 o differential output data d6 and d7 multiplexed, complement d6_d7_p 24 o differential output data d6 and d7 multiplexed, true d4_d5_m 25 o differential output data d4 and d5 multiplexed, complement d4_d5_p 26 o differential output data d4 and d5 multiplexed, true d2_d3_m 27 o differential output data d2 and d3 multiplexed, complement d2_d3_p 28 o differential output data d2 and d3 multiplexed, true d0_d1_m 29 o differential output data d0 and d1 multiplexed, complement table 2. pin description (cmos digital outputs) symbol pin type [1] description
ADC1415S_ser_3 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. preliminary data sheet rev. 03 ? 12 april 2010 6 of 39 nxp semiconductors ADC1415S series ADC1415S series; input buffer; cmos or lvds ddr digital outputs [1] pins 1 to 16 and pins 33 to 40 are the same for both cmos and lvds ddr outputs (see table 2 ) [2] p: power supply; g: ground; i: input; o: output; i/o: input/output. 7. limiting values 8. thermal characteristics [1] value for six layers board in still ai r with a minimum of 25 thermal vias. d0_d1_p 30 o differential output data d0 and d1 multiplexed, true davm 31 o data valid output clock, complement davp 32 o data valid output clock, true table 3. pin description ?continued (lvds/ddr) digital outputs) symbol pin [1] type [2] description table 4. limiting values in accordance with the absolute maximum rating system (iec 60134). symbol parameter conditions min max unit v o output voltage pins d13 to d0 or pins d13p to d0p and d13m to d0m ? 0.4 +3.9 v v dda(3v) analog supply voltage 3 v on pin vdda3v ? 0.4 +4.6 v v dda(5v) analog supply voltage 5 v on pin vdda5v ? 0.5 +6.0 v v ddo output supply voltage ? 0.4 +4.6 v v cc supply voltage difference v dda(3v) ? v ddo v t stg storage temperature ? 55 +125 c t amb ambient temperature ? 40 +85 c t j junction temperature - 125 c table 5. thermal characteristics symbol parameter conditions typ unit r th(j-a) thermal resistance from junction to ambient [1] 30.5 k/w r th(j-c) thermal resistance from junction to case [1] 13.3 k/w
ADC1415S_ser_3 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. preliminary data sheet rev. 03 ? 12 april 2010 7 of 39 nxp semiconductors ADC1415S series ADC1415S series; input buffer; cmos or lvds ddr digital outputs 9. static characteristics table 6. static characteristics [1] symbol parameter conditions min typ max unit supplies v dda(5v) analog supply voltage 5 v 4.75 5.0 5.25 v v dda(3v) analog supply voltage 3 v 2.85 3.0 3.4 v v ddo output supply voltage cmos mode 1.65 1.8 3.6 v lvds ddr mode 2.85 3.0 3.6 v i dda(5v) analog supply current 5 v f clk =125msps; f i =70 mhz -46-ma i dda(3v) analog supply current 3 v f clk =125msps; f i =70 mhz -205-ma i ddo output supply current cmos mode; f clk =125msps; f i =70 mhz -14-ma lvds ddr mode: f clk =125msps; f i =70 mhz -43-ma p power dissipation ADC1415S125; analog supply only -840-mw ADC1415S105; analog supply only -770-mw ADC1415S080; analog supply only -635-mw ADC1415S065; analog supply only -580-mw power-down mode - 2 - mw standby mode - 40 - mw clock inputs: pins clkp and clkm lvpecl v i(clk)dif differential clock input voltage peak-to-peak 1.6 - v lvds v i(clk)dif differential clock input voltage peak-to-peak - 0.7 - v sine wave v i(clk)dif differential clock input voltage peak-to-peak 0.8 3.0 - v lvcmos v il low-level input voltage - - 0.3v dda(3v) v v ih high-level input voltage 0.7v dda(3v) --v logic inputs: pins pwd and oe v il low-level input voltage 0 - 0.8 v v ih high-level input voltage 2 - v dda(3v) v i il low-level input current - a i ih high-level input current ? 10 - +10 a
ADC1415S_ser_3 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. preliminary data sheet rev. 03 ? 12 april 2010 8 of 39 nxp semiconductors ADC1415S series ADC1415S series; input buffer; cmos or lvds ddr digital outputs serial peripheral interface: pins cs , sdio/ods, sclk/dfs v il low-level input voltage 0 - 0.3v dda(3v) v v ih high-level input voltage 0.7v dda(3v) -v dda(3v) v i il low-level input current ? 10 - +10 a i ih high-level input current ? 50 - +50 a c i input capacitance - 4 - pf digital outputs, cmos mode: pins d13 to d0, otr, dav output levels, v ddo =3v v ol low-level output voltage i ol = ognd - 0.2v ddo v v oh high-level output voltage i oh = 0.8v ddo -v ddo v i ol low-level output current 3-state; output level = 0 v -- a i oh high-level output current 3-state; output level = v dda(3v) -- a c o output capacitance high impedance; oe =high -3-pf output levels, v ddo =1.8v v ol low-level output voltage i ol = ognd - 0.2v ddo v v oh high-level output voltage i oh = 0.8v ddo -v ddo v digital outputs, lvds mode: pins d13p to d0p, d13m to d0m, davp and davm output levels, v ddo = 3 v only, r load =100 v o(offset) output offset voltage output buffer current set to 3.5 ma -1.2-v v o(dif) differential output voltage output buffer current set to 3.5 ma -350-mv c o output capacitance - - pf analog inputs: pins inp and inm i i input current ? 5- +5 a r i input resistance - 550 - c i input capacitance - 1.3 - pf v i(cm) common-mode input voltage v inp =v inm 0.9 1.5 2 v b i input bandwidth - 600 - mhz v i(dif) differential input voltage peak-to-peak 1 2 v common mode output voltage: pin vcm v o(cm) common-mode output voltage - 0.5v dda(3v) -v i o(cm) common-mode output current - - a table 6. static characteristics [1] ?continued symbol parameter conditions min typ max unit
ADC1415S_ser_3 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. preliminary data sheet rev. 03 ? 12 april 2010 9 of 39 nxp semiconductors ADC1415S series ADC1415S series; input buffer; cmos or lvds ddr digital outputs [1] typical values measured at v dda(3v) =3v, v ddo = 1.8 v, v dda(5v) =5v; t amb =25 c and c l = 5 pf; minimum and maximum values are across the full temperature range t amb = ? 40 c to +85 c at v dda(3v) =3v, v ddo = 1.8 v, v dda(5v) =5v, v inp ? v inm = ? 1 dbfs; internal reference mode; applied to cmos and lvds interface; unles s otherwise specified. i/o reference voltage: pin vref v vref voltage on pin vref output - 0.5 to 1 - v input 0.5 - 1 v accuracy inl integral non-linearity ? 5 1+5lsb dnl differential non-linearity guaranteed no missing codes ? 0.95 0.5 +0.95 lsb e offset offset error - 2- mv e g gain error - 0.5 - %fs supply psrr power supply rejection ratio 100 mv (p-p) on v dda(3v) -35-dbc table 6. static characteristics [1] ?continued symbol parameter conditions min typ max unit
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx ADC1415S_ser_3 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. preliminary data sheet rev. 03 ? 12 april 2010 10 of 39 nxp semiconductors ADC1415S series ADC1415S series; input buffer; cmos or lvds ddr digital outputs 10. dynamic characteristics 10.1 dynamic characteristics table 7. dynamic characteristics [1] symbol parameter conditions ADC1415S065 ADC1415S080 ADC1415S105 ADC1415S125 unit min typ max min typ max min typ max min typ max analog signal processing 2h second harmonic level f i =3mhz -87--87--86--88-dbc f i =30mhz -86--86--86--87-dbc f i =70mhz -85--85--84--85-dbc f i =170mhz -82--82--81--83-dbc 3h third harmonic level f i =3mhz -86--86--85--87-dbc f i =30mhz -85--85--85--86-dbc f i =70mhz -84--84--83--84-dbc f i =170mhz -81--81--80--82-dbc thd total harmonic distortion f i =3mhz -85--85--84--86-dbc f i =30mhz -84--84--84--85-dbc f i =70mhz -83--83--82--83-dbc f i =170mhz -80--80--79--81-dbc enob effective number of bits f i = 3 mhz - 11.7 - - 11.7 - - 11.6 - - 11.6 - bits f i = 30 mhz - 11.6 - - 11.5 - - 11.5 - - 11.5 - bits f i = 70 mhz - 11.5 - - 11.5 - - 11.4 - - 11.4 - bits f i = 170 mhz - 11.4 - - 11.4 - - 11.3 - - 11.3 - bits snr signal-to- noise ratio f i = 3 mhz - 72.1 - - 72.0 - - 71.8 - - 71.4 - dbfs f i = 30 mhz - 71.3 - - 71.2 - - 71.2 - - 71.1 - dbfs f i = 70 mhz - 70.7 - - 70.7 - - 70.6 - - 70.5 - dbfs f i = 170 mhz - 70.2 - - 70.1 - - 70.0 - - 69.9 - dbfs sfdr spurious- free dynamic range f i =3mhz -86--86--85--87-dbc f i =30mhz -85--85--85--86-dbc f i =70mhz -84--84--83--84-dbc f i =170mhz -81--81--80--82-dbc
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx ADC1415S_ser_3 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. preliminary data sheet rev. 03 ? 12 april 2010 11 of 39 nxp semiconductors ADC1415S series ADC1415S series; input buffer; cmos or lvds ddr digital outputs [1] typical values measured at v dda(3v) =3v, v ddo = 1.8 v, v dda(5v) =5v; t amb =25 c and c l = 5 pf; minimum and maximum values are across the full temperature range t amb = ? 40 c to +85 c at v dda(3v) =3v, v ddo =1.8v, v dda(5v) =5v, v inp ? v inm = ? 1 dbfs; internal reference mode; applied to cmos and lvds interface; unless otherwise specified. imd intermodul- ation distortion f i =3mhz -89--89--88--89-dbc f i =30mhz -88--88--88--88-dbc f i =70mhz -87--87--86--86-dbc f i =170mhz -84--85--83--84-dbc table 7. dynamic characteristics [1] ?continued symbol parameter conditions ADC1415S065 ADC1415S080 ADC1415S105 ADC1415S125 unit min typ max min typ max min typ max min typ max
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx ADC1415S_ser_3 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. preliminary data sheet rev. 03 ? 12 april 2010 12 of 39 nxp semiconductors ADC1415S series ADC1415S series; input buffer; cmos or lvds ddr digital outputs 10.2 clock and digital output timing table 8. clock and digital outp ut timing characteristics [1] symbol parameter conditions ADC1415S065 ADC1415S080 ADC1415S105 ADC1415S125 unit min typ max min typ max min typ max min typ max clock timing input: pins clkp and clkm f clk clock frequency 20 - 65 60 - 80 75 - 105 100 - 125 mhz t lat(data) data latency time -14--14--14--14-clock cycle clk clock duty cycle dcs_en = 1 30 50 70 30 50 70 30 50 70 30 50 70 % dcs_en = 0455055455055455055455055% t d(s) sampling delay time -0.8--0.8--0.8--0.8-ns t wake wake-up time -tbd--tbd--tbd--tbd-ns cmos mode timing output: pins d13 to d0 and dav t pd propagation delay data -3.9--3.9--3.9--3.9-ns dav -4.2--4.2--4.2--4.2-ns t su set-up time -7.7--6.5--4.7--4.3-ns t h hold time -6.7--5.5--3.8--3.5-ns t r rise time [2] data 0.5- 2.40.5- 2.40.5- 2.40.5- 2.4ns dav 0.5 - 2.4 0.5 - 2.4 0.5 - 2.4 0.5 - 2.4 ns t f fall time [2] data 0.5- 2.40.5- 2.40.5- 2.40.5- 2.4ns
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx ADC1415S_ser_3 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. preliminary data sheet rev. 03 ? 12 april 2010 13 of 39 nxp semiconductors ADC1415S series ADC1415S series; input buffer; cmos or lvds ddr digital outputs [1] typical values measured at v dda(3v) =3v, v ddo = 1.8 v, v dda(5v) =5v; t amb =25 c and c l = 5 pf; minimum and maximum values are across the full temperature range t amb = ? 40 c to +85 c at v dda(3v) =3v, v ddo =1.8v, v dda(5v) =5v, v inp ? v inm = ? 1 dbfs; internal reference mode; applied to cmos and lvds interface; unless otherwise specified. [2] measured between 20 % to 80 % of v ddo . [3] rise time measured from ? 50 mv to +50 mv; fall time measured from +50 mv to ? 50 mv. lvds ddr mode timing outpu t: pins d13p to d0p, d13m to d0m, davp and davm t pd propagation delay data -3.9--3.9--3.9--3.9-ns dav -4.2--4.2--4.2--4.2-ns t su set-up time -5.1--3.5--2,1--1.4-ns t h hold time -2.0--2.0--2.0--2.0-ns t r rise time [3] data 50 100 200 50 100 200 50 100 200 50 100 200 ps dav 50 100 200 50 100 200 50 100 200 50 100 200 ps t f fall time [3] data 50 100 200 50 100 200 50 100 200 50 100 200 ps dav 50 100 200 50 100 200 50 100 200 50 100 200 ps table 8. clock and digital outp ut timing characteristics [1] ?continued symbol parameter conditions ADC1415S065 ADC1415S080 ADC1415S105 ADC1415S125 unit min typ max min typ max min typ max min typ max
ADC1415S_ser_3 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. preliminary data sheet rev. 03 ? 12 april 2010 14 of 39 nxp semiconductors ADC1415S series ADC1415S series; input buffer; cmos or lvds ddr digital outputs fig 4. cmos mode timing fig 5. ldvs ddr mode timing (n ? 12) t d(s) t clk n n + 1 n + 2 t clk t su t pd t h t pd clkp clkm data dav 005aaa06 0 (n ? 11) (n ? 13) (n ? 14) 005aaa061 (n ? 14) t d(s) t clk n n + 1 n + 2 clkp clkm davp davm t su t h t h t su t pd t pd d x _d x + 1 _p d x _d x + 1 _m d x d x + 1 d x + 1 d x + 1 d x + 1 d x + 1 d x d x d x d x (n ? 11) (n ? 12) (n ? 13) t clk
ADC1415S_ser_3 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. preliminary data sheet rev. 03 ? 12 april 2010 15 of 39 nxp semiconductors ADC1415S series ADC1415S series; input buffer; cmos or lvds ddr digital outputs 10.3 spi timings [1] typical values measured at v dda(3v) =3v, v ddo = 1.8 v, v dda(5v) =5v; t amb =25 c and c l =5pf; minimum and maximum values are across the full temperature range t amb = ? 40 c to +85 c at v dda(3v) =3v, v ddo = 1.8 v, v dda(5v) =5v, v inp ? v inm = ? 1 dbfs; internal reference mode; applied to cmos and lvds interface; unless otherwise specified table 9. characteristics symbol parameter conditions min typ max unit spi timings t w(sclk) sclk pulse width 40 - - ns t w(sclkh) sclk pulse width high 16 - - ns t w(sclkl) sclk pulse width low 16 - - ns t su set-up time data to sclkh 5 - - ns cs to sclkh 5 - - ns t h hold time data to sclkh 2 - - ns cs to sclkh 2 - - ns f clk(max) maximum clock frequency - - 25 mhz fig 6. spi timing t su sdio sclk r/w w1 w0 a12 a11 d2 d1 d0 t su t h t h t w(sclk) 005aaa06 5 cs t w(sclkl) t w(sclkh)
ADC1415S_ser_3 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. preliminary data sheet rev. 03 ? 12 april 2010 16 of 39 nxp semiconductors ADC1415S series ADC1415S series; input buffer; cmos or lvds ddr digital outputs 11. application information 11.1 device control the ADC1415S can be controlled via the serial peripheral interface (spi control mode) or directly via the i/o pins (pin control mode). 11.1.1 spi and pin control modes the device enters pin control mode at power-up, and remains in this mode as long as pin cs is held high. in pin control mode, the spi pins sdio, cs and sclk are used as static control pins. spi control mode is enabled by forcing pin cs low. once spi control mode has been enabled, the device will remain in this mode. the transition from pin control mode to spi control mode is illustrated in figure 7 . when the device enters spi control mode, the output data standard and data format are determined by the level on pin sdio as soon as a transition is triggered by a falling edge on cs . 11.1.2 operating mode selection the active ADC1415S operating mode (power-u p, power-down or sleep) can be selected via the spi interface (see ta b l e 1 9 ) or using pins pwd and oe in pin control mode, as described in table 10 . 11.1.3 selecting the output data standard the output data standard (cmos or lvds ddr) can be selected via the spi interface (see ta b l e 2 3 ) or using pin ods in pin control mode . lvds ddr is selected when ods is high, otherwise cmos is selected. fig 7. control mode selection. r/w spi control mode pin control mode data format offset binary data format two's complement lvds ddr sdio/ods sclk/dfs w1 w0 a12 005aaa03 9 cmos cs table 10. operating mode selection via pin pwd and oe pin pwd pin oe operating mode output high-z 0 0 power-up no 0 1 power-up yes 1 0 sleep yes 1 1 power-down yes
ADC1415S_ser_3 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. preliminary data sheet rev. 03 ? 12 april 2010 17 of 39 nxp semiconductors ADC1415S series ADC1415S series; input buffer; cmos or lvds ddr digital outputs 11.1.4 selecting the output data format the output data format can be selected via the spi interface (offset binary, two?s complement or gray code; see ta b l e 2 3 ) or using pin dfs in pin control mode (offset binary or two?s complement). offset binary is selected when dfs is low. when dfs is high, two?s complement is selected. 11.2 analog inputs 11.2.1 input stage the analog input of the ADC1415S supports di fferential or single-ended input drive. optimal performance is achieved using differen tial inputs. the adc inputs are internally biased and need to be decoupled. the full scale analog input voltage range is configurable between 1 v (p-p) and 2 v (p-p) via a programmable internal reference (see section 11.3 and table 21 further details). the equivalent circuit of the input buffer followed by the sample and hold (s/h) input stage, including electrostatic discharge (esd) protection and circuit and package parasitics, is shown in figure 8 . the integrated input buffer offers the following advantages: ? the kickback effect is avoided - the charge injection and glitches generated by the s/h input stage are isolated from the input ci rcuitry. so there?s no need for additional filtering. ? the input capacitance is very low and constant over a wide frequency range, which makes the ADC1415S easy to drive. fig 8. input sampling circuit and input buffer 005aaa10 7 inp package esd parasitics switch r on = 15 4 pf 4 pf sampling capacitor sampling capacitor switch r on = 15 inm 8 7 internal clock internal clock input buffer
ADC1415S_ser_3 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. preliminary data sheet rev. 03 ? 12 april 2010 18 of 39 nxp semiconductors ADC1415S series ADC1415S series; input buffer; cmos or lvds ddr digital outputs the sample phase occurs when the internal clock (derived from the clock signal on pin clkp/clkm) is high. the voltage is then he ld on the sampling capacitors. when the clock signal goes low, the stage enters the hold phase and the voltage information is transmitted to the adc core. 11.2.2 transformer the configuration of the transf ormer circuit is determined by the input frequency. the configuration shown in figure 9 would be suitable for a baseband application. the configuration shown in figure 10 is recommended for high frequency applications. in both cases, the choice of transforme r will be a compromise between cost and performance. fig 9. single transformer configuration suitable for baseband applications fig 10. dual transformer configuration suitable for high intermediate frequency application 005aaa10 8 100 nf 100 nf 100 nf 100 nf inp inm vcm analog input adt1-1wt 100 nf 100 nf 50 005aaa10 9 100 nf 100 nf 100 nf inp inm 100 50 50 adt1-1wt adt1-1wt analog input 100 nf 100 nf vcm 100 nf
ADC1415S_ser_3 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. preliminary data sheet rev. 03 ? 12 april 2010 19 of 39 nxp semiconductors ADC1415S series ADC1415S series; input buffer; cmos or lvds ddr digital outputs 11.3 system reference and power management 11.3.1 internal/external references the ADC1415S has a stable and accurate built-i n internal reference vo ltage to adjust the adc full-scale. this reference voltage can be se t internally via spi or with pins vref and sense (programmable in 1 db steps between 0 db and ? 6 db via control bits intref[2:0] when bit intref_en = 1; see table 21 ). see figure 12 , figure 13 , figure 14 and figure 15 ). the equivalent reference circuit is shown in figure 11 . external reference is also possible by providing a voltage on pin vref as described in figure 14 . if bit intref_en is set to 0, the reference volt age will be determined either internally or externally as detailed in ta b l e 11 . [1] the voltage on pin vref is doubled internally to generate the internal reference voltage. fig 11. reference equivalent schematic table 11. reference selection selection spi bit intref_en sense pin vref pin full scale (p-p) internal ( figure 12 ) 0 agnd 330 pf capacitor to agnd 2 v internal ( figure 13 ) 0 pin vref connected to pin sense and via a 330 pf capacitor to agnd 1 v external ( figure 14 ) 0v dda(3v) external voltage between 0.5 v and 1 v [1] 1 v to 2 v internal via spi ( figure 15 ) 1 pin vref connected to pin sense and via 330 pf capacitor to agnd 1 v to 2 v ext_ref ext_ref 005aaa164 reft refb sense vref selection logic bandgap reference adc core buffer reference amp
ADC1415S_ser_3 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. preliminary data sheet rev. 03 ? 12 april 2010 20 of 39 nxp semiconductors ADC1415S series ADC1415S series; input buffer; cmos or lvds ddr digital outputs figure 12 to figure 15 illustrate how to conne ct the sense and vref pins to select the required reference voltage source. 11.3.2 reference gain control the reference gain is programmable between 0 db to ? 6 db in 1 db steps via the spi (see ta b l e 2 1 ). the corresponding full-scale input voltage range varies between 2 v (p-p) and 1 v (p-p), as shown in ta b l e 1 2 : 11.3.3 common-mode output voltage (v o(cm) ) a 0.1 f filter capacitor should be connected between pin vcm and ground. fig 12. internal reference, 2 v (p-p) full scale fig 13. internal reference, 1 v (p-p) full scale fig 14. external reference, 1 v (p-p) to 2 v (p-p) full-scale fig 15. internal reference vi a spi, 1 v (p-p) to 2 v (p-p) full-scale 330 pf vref sense 005aaa11 6 reference equivalent schematic 330 pf 005aaa11 7 vref sense reference equivalent schematic 0.1 f vdda v 005aaa11 9 vref sense reference equivalent schematic reference equivalent schematic 330 pf 005aaa11 8 vref sense table 12. reference spi gain control intref gain full scale (p-p) 000 0 db 2 v 001 ? 1db 1.78v 010 ? 2db 1.59v 011 ? 3db 1.42v 100 ? 4db 1.26v 101 ? 5db 1.12v 110 ? 6db 1v 111 reserved x
ADC1415S_ser_3 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. preliminary data sheet rev. 03 ? 12 april 2010 21 of 39 nxp semiconductors ADC1415S series ADC1415S series; input buffer; cmos or lvds ddr digital outputs 11.3.4 biasing the common-mode input voltage (v i(cm) ) on pins inp and inm is set internally. the input buffer bias current can be set to one of three levels (high, medium or low) via the spi (see ta b l e 2 2 ). 11.4 clock input 11.4.1 drive modes the ADC1415S can be driven differentially (s ine, lvpecl or lvds) with little or no degradation on dynamic performances. it ca n also be driven by a single-ended lvcmos signal connected to pin clkp (clkm should be connected to ground via a capacitor) or clkm (clkp should be connected to ground via a capacitor). a. rising edge lvcmos b. falling edge lvcmos fig 16. lvcmos single-ended clock input a. sine clock input b. sine clock input (with transformer) c. lvds clock input d. lvpecl clock input fig 17. differential clock input lvcmos clock input clkp clkm 005aaa17 4 005aaa05 3 lvcmos clock input clkp clkm sine clock input clkp clkm 005aaa17 3 sine clock input clkp clkm 005aaa05 4 005aaa05 5 lvds clock input clkp clkm lvpecl clock input 005aaa17 2 clkp clkm
ADC1415S_ser_3 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. preliminary data sheet rev. 03 ? 12 april 2010 22 of 39 nxp semiconductors ADC1415S series ADC1415S series; input buffer; cmos or lvds ddr digital outputs 11.4.2 equivalent input circuit the equivalent circuit of the input clock buffer is shown in figure 18 . the common-mode voltage of the differential input stage is set via internal 5 k resistors. single-ended or differential clock inputs c an be selected via the spi interface (see ta b l e 2 0 ). if single-ended is enabled, the input pin (clkm or clkp) is selected via control bit se_sel. if single-ended is implemented without setting se_sel to the appropriate value, the unused pin should be connected to ground via a capacitor. 11.4.3 duty cycle stabilizer the duty cycle stabilizer can improve th e overall performances of the adc by compensating the duty cycle of the input clock signal. when the duty cycle stabilizer is active (bit dcs_en = 1; see ta b l e 2 0 ), the circuit can handle sign als with duty cycles of between 30 % and 70 % (typical). when the duty cycle stabilizer is disabled (dcs_en = 0), the input clock signal should have a duty cycle of between 45% and 55%. 11.4.4 clock input divider the ADC1415S contains an input clock divider that divides the incoming clock by a factor of 2 (when bit clkdiv = 1; see ta b l e 2 0 ). this feature allows the user to deliver a higher clock frequency with better jitter performance, leading to a better snr result once acquisition has been performed. fig 18. equivalent input circuit clkp clkm 005aaa05 6 package esd parasitics 5 k 5 k v cm(clk) se_sel se_sel
ADC1415S_ser_3 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. preliminary data sheet rev. 03 ? 12 april 2010 23 of 39 nxp semiconductors ADC1415S series ADC1415S series; input buffer; cmos or lvds ddr digital outputs 11.5 digital outputs 11.5.1 digital output buffers: cmos mode the digital output buffers can be configured as cmos by setting bit lvds/cmos to 0 (see table 23 ). each digital output has a dedicated output buffer. the equivalent circuit of the cmos digital output buffer is shown in figure 19 . the buffer is powered by a separate ognd/v ddo to ensure 1.8 v to 3.3 v compatibilit y and is isolated from the adc core. each buffer can be loaded by a maximum of 10 pf. the output resistance is 50 and is the combination of the an internal resistor and the equivalent output resistance of the buffer. there is no need for an external damping resistor. the drive strength of both data and dav buffers can be programmed via the spi in order to adjust the rise and fall times of the output digital signals (see ta b l e 3 0 ): fig 19. cmos digital output buffer vddo esd package parasitics ognd dx 005aaa057 50 logic driver
ADC1415S_ser_3 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. preliminary data sheet rev. 03 ? 12 april 2010 24 of 39 nxp semiconductors ADC1415S series ADC1415S series; input buffer; cmos or lvds ddr digital outputs 11.5.2 digital output buffers: lvds ddr mode the digital output buffers can be configured as lvds ddr by setting bit lvds/cmos to 1 (see table 23 ). each output should be terminated externally with a 100 resistor (typical) at the receiver side ( figure 20 ) or internally via spi contro l bits lvds_int_ter[2:0] (see figure 21 and ta b l e 3 2 ). the default lvds ddr output bu ffer current is set to 3.5 m a. it can be programmed via the spi (bits davi[1:0] and datai[1:0]; see ta b l e 3 1 ) in order to adjust the output logic voltage levels. fig 20. lvds ddr digital output buffer - externally terminated fig 21. lvds ddr digital output buffer - internally terminated table 13. lvds ddr output register 2 lvds_int_ter[2:0] resistor value ( ) 000 no internal termination 001 300 010 180 011 110 100 150 vcco 3.5 ma typ d n p/d n + 1 p d n m/d n + 1 m ognd 100 ? 005aaa05 8 + ? + receiver vcco ognd 005aaa05 9 d x p/d x + 1 p d x m/d x + 1 m 100 3.5 ma typ + ? + ? receiver
ADC1415S_ser_3 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. preliminary data sheet rev. 03 ? 12 april 2010 25 of 39 nxp semiconductors ADC1415S series ADC1415S series; input buffer; cmos or lvds ddr digital outputs 11.5.3 data valid (dav) output clock a data valid output clock signal (dav) is pr ovided that can be used to capture the data delivered by the ADC1415S. detailed timing diagrams for cmos and lvds ddr modes are provided in figure 4 and figure 5 respectively. 11.5.4 out-of-range (otr) an out-of-range signal is provided on pin otr. the latency of otr is fourteen clock cycles. the otr response can be speeded up by enabling fast otr (bit fastotr = 1; see ta b l e 2 9 ). in this mode, the latency of otr is reduced to only four clock cycles. the fast otr detection threshold (below full scale) can be programmed via bits fastotr_det[2:0]. 11.5.5 digital offset by default, the ADC1415S delivers output code that corresponds to the analog input. however it is possible to add a digital offset to the output code via the spi (bits dig_offset[5:0]; see ta b l e 2 5 ). 11.5.6 test patterns for test purposes, the ADC1415S can be configured to transmit one of a number of predefined test patterns (via bits testpat_sel[2:0]; see ta b l e 2 6 ). a custom test pattern can be defined by the user (testpat_user; see ta b l e 2 7 and ta b l e 2 8 ) and is selected when testpat_sel[2:0] = 101. the selected test pattern will be transmitted regardless of the analog input. 101 100 110 81 111 60 table 13. lvds ddr output register 2 ?continued lvds_int_ter[2:0] resistor value ( ) table 14. fast otr register fastotr_det[2:0] detection level (db) 000 ? 20.56 001 ? 16.12 010 ? 11.02 011 ? 7.82 100 ? 5.49 101 ? 3.66 110 ? 2.14 111 ? 0.86
ADC1415S_ser_3 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. preliminary data sheet rev. 03 ? 12 april 2010 26 of 39 nxp semiconductors ADC1415S series ADC1415S series; input buffer; cmos or lvds ddr digital outputs 11.5.7 output codes versus input voltage 11.6 serial peripheral interface (spi) 11.6.1 register description the ADC1415S serial interface is a synchronous serial communications port that allows for easy interfacing with many commonly-used microprocessors. it provides access to the registers that control the operation of the chip. this interface is configured as a 3- wire type (sdio as bidirectional pin) pin sclk is the serial clock input and cs is the chip select pin. each read/write operation is initiated by a low level on cs . a minimum of three bytes will be transmitted (two instruction bytes and at least one data byte). the number of data bytes is determined by the value of bits w1 and w2 (see table 17 ). [1] bit r/w indicates whether it is a read (1) or a write (0) operation. [2] bits w1 and w0 indicate the number of bytes to be transferred after the instruction byte (see table 17 ). table 15. output codes v inp ? v inm offset binary two?s complement otr pin < ? 1 00 0000 0000 0000 10 0000 0000 0000 1 ? 1 00 0000 0000 0000 10 0000 0000 0000 0 ? 0.9998779 00 0000 0000 0001 10 0000 0000 0001 0 ? 0.9997559 00 0000 0000 0010 10 0000 0000 0010 0 ? 0.9996338 00 0000 0000 0011 10 0000 0000 0011 0 ? 0.9995117 00 0000 0000 0100 10 0000 0000 0100 0 .... .... .... 0 ? 0.0002441 01 1111 1111 1110 11 1111 1111 1110 0 ? 0.0001221 01 1111 1111 1111 11 1111 1111 1111 0 0 10 0000 0000 0000 00 0000 0000 0000 0 +0.0001221 10 0000 0000 0001 00 0000 0000 0001 0 +0.0002441 10 0000 0000 0010 00 0000 0000 0010 0 .... .... .... 0 +0.9995117 11 1111 1111 1011 01 1111 1111 1011 0 +0.9996338 11 1111 1111 1100 01 1111 1111 1100 0 +0.9997559 11 1111 1111 1101 01 1111 1111 1101 0 +0.9998779 11 1111 1111 1110 01 1111 1111 1110 0 +1 11 1111 1111 1111 01 1111 1111 1111 0 > +1 11 1111 1111 1111 01 1111 1111 1111 1 table 16. instruction bytes for the spi msb lsb bit 76543210 description r/w [1] w1 [2] w0 [2] a12 a11 a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0
ADC1415S_ser_3 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. preliminary data sheet rev. 03 ? 12 april 2010 27 of 39 nxp semiconductors ADC1415S series ADC1415S series; input buffer; cmos or lvds ddr digital outputs bits a12 to a0 indicate the address of the register being accessed. in the case of a multiple byte transfer, this address is the first register to be accessed. an address counter is increased to access subsequent addresses. the steps involved in a data transfer are as follows: 1. a falling edge on cs in combination with a rising edge on sclk determine the start of communications. 2. the first phase is the transfer of the 2-byte instruction. 3. the second phase is the transfer of the da ta which can vary in length but will always be a multiple of 8 bits. the msb is always sent first (for instruction and data bytes). 4. a rising edge on cs indicates the end on data transmission. 11.6.2 default modes at start-up during circuit initialization, it does no t matter which output data standard has been selected. at power-up, the dev ice enters pin control mode. a falling edge on cs will trigger a transition to spi co ntrol mode. when the ADC1415S enters spi control mo de, the output data standard (cmo s/lvds ddr) is determined by the level on pin sdio (see figure 23 ). once in spi control mode, the output data standard can be changed via bit lvds/cmos in table 23 . when the ADC1415S enters spi control mode, th e output data format (two?s complement or offset binary) is determined by the level on pin sclk (gray code can only be selected via the spi). once in spi control mode, the output data format can be changed via bit data_format[1:0] in ta b l e 2 3 . table 17. number of data bytes to be transferred after the instruction bytes w1 w0 number of bytes transmitted 001 byte 012 bytes 103 bytes 1 1 4 bytes or more fig 22. spi mode timing sclk sdio r/w w1 w0 a12 a11 a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 d7 d6 d5 d4 d3 d2 d1 d3 d2 d1 d0 d0 d7 d6 d5 d4 instruction bytes register n (data) register n + 1 (data) 005aaa06 2 cs
ADC1415S_ser_3 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. preliminary data sheet rev. 03 ? 12 april 2010 28 of 39 nxp semiconductors ADC1415S series ADC1415S series; input buffer; cmos or lvds ddr digital outputs fig 23. default mode at start-up: sclk low = offset binary; sdio high = lvds ddr fig 24. default mode at start-up: sclk high = two?s complement; sdio low = cmos cs sdio (cmos lvds ddr) sclk (data format) offset binary, lvds ddr default mode at start-up 005aaa06 3 sdio (cmos lvds ddr) sclk (data format) two's complement, cmos default mode at start-up 005aaa06 4 cs
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx ADC1415S_ser_3 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. preliminary data sheet rev. 03 ? 12 april 2010 29 of 39 nxp semiconductors ADC1415S series ADC1415S series; input buffer; cmos or lvds ddr digital outputs 11.6.3 register allocation map table 18. register allocation map addr hex register name r/w bit definition default bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 bin 0005 reset and operating mode r/w sw_rst reserved[2:0] - - op_mode[1:0] 0000 0000 0006 clock r/w - - - se_sel diff_se - clkdiv dcs_en 0000 0001 0008 internal reference r/w - - - - intref_en intref[2:0] 0000 0000 0010 input buffer r/w - - - - - - ib_ibias[1:0] 0000 0011 0011 output data standard. r/w - - - lvds_cmo s outbuf outbus_swap data_format[1:0] 0000 0000 0012 output clock r/w - - - - davinv davphase[2:0] 0000 1110 0013 offset r/w - - dig_offset[5:0] 0000 0000 0014 test pattern 1 r/w - - - - - testpat_sel[2:0] 0000 0000 0015 test pattern 2 r/w testpat_user[13:6] 0000 0000 0016 test pattern 3 r/w testpat_user[5:0] - - 0000 0000 0017 fast otr r/w - - - - fastotr fastotr_det[2:0] 0000 0000 0020 cmos output r/w - - - - dav_drv[1:0] data_drv[1:0] 0000 1110 0021 lvds ddr o/p 1 r/w - - davi_x2_e n davi[1:0] datai_x2_en datai[1:0] 0000 0000 0022 lvds ddr o/p 2 r/w - - - - bit_byte_wis e lvds_int_ter[2:0] 0000 0000
ADC1415S_ser_3 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. preliminary data sheet rev. 03 ? 12 april 2010 30 of 39 nxp semiconductors ADC1415S series ADC1415S series; input buffer; cmos or lvds ddr digital outputs table 19. reset and operating mode control register (address 0005h) bit description bit symbol access value description 7 sw_rst r/w reset digital section 0 no reset 1 performs a reset on spi registers 6 to 4 reserved[2:0] 000 reserved 3 to 2 - 00 not used 1 to 0 op_mode[1:0] r/w operating mode 00 normal (power-up) 01 power-down 10 sleep 11 normal (power-up) table 20. clock control register (address 0006h) bit description bit symbol access value description 7 to 5 - 000 not used 4 se_sel r/w single-ended clock input pin select 0 clkm 1clkp 3 diff_se r/w differential/single ended clock input select 0 fully differential 1 single-ended 2 - 0 not used 1 clkdiv r/w clock input divide by 2 0 disabled 1 enabled 0 dcs_en r/w duty cycle stabilizer 0 disabled 1 enabled
ADC1415S_ser_3 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. preliminary data sheet rev. 03 ? 12 april 2010 31 of 39 nxp semiconductors ADC1415S series ADC1415S series; input buffer; cmos or lvds ddr digital outputs table 21. internal reference control register (address 0008h) bit description bit symbol access value description 7 to 4 - 0000 not used 3 intref_en r/w programmable internal reference enable 0 disable 1 active 2 to 0 intref[2:0] r/w programmable internal reference 000 0db (fs=2v) 001 ? 1db (fs=1.78v) 010 ? 2db (fs=1.59v) 011 ? 3db (fs=1.42v) 100 ? 4db (fs=1.26v) 101 ? 5db (fs=1.12v) 110 ? 6db (fs=1v) 111 reserved table 22. input buffer control regist er (address 0010h) bit description bit symbol access value description 7 to 2 - 000000 not used 1 to 0 ib_ibias[1:0] r/w input buffer bias current 00 not used 01 medium 10 low 11 high table 23. output data standard control register (address 0011h) bit description bit symbol access value description 7 to 5 - 000 not used 4 lvds_cmos r/w output data standard: lvds ddr or cmos 0 cmos 1 lvds ddr 3 outbuf r/w output buffers enable 0 output enabled 1 output disabled (high z) 2 outbus_swap r/w output bus swapping 0 no swapping 1 output bus is swapped (msb becomes lsb and vice versa) 1 to 0 data_format[1:0] r/w output data format 00 offset binary 01 two?s complement 10 gray code 11 offset binary
ADC1415S_ser_3 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. preliminary data sheet rev. 03 ? 12 april 2010 32 of 39 nxp semiconductors ADC1415S series ADC1415S series; input buffer; cmos or lvds ddr digital outputs table 24. output clock register (address 0012h) bit description bit symbol access value description 7 to 4 - 0000 not used 3 davinv r/w output clock data valid (dav) polarity 0normal 1 inverted 2 to 0 davphase[2:0] r/w dav phase select 000 output clock shifted (ahead) by 3 ns 001 output clock shifted (ahead) by 2.5 ns 010 output clock shifted (ahead) by 2 ns 011 output clock shifted (ahead) by 1.5 ns 100 output clock shifted (ahead) by 1 ns 101 output clock shifted (ahead) by 0.5 ns 110 default value as defined in timing section 111 output clock shifted (delayed) by 0.5 ns table 25. offset register (add ress 0013h) bit description bit symbol access value description 7 to 6 - 00 not used 5 to 0 dig_offset[5:0] r/w digital offset adjustment 011111 +31 lsb ... ... 000000 0 ... ... 100000 ? 32 lsb table 26. test pattern register 1 (address 0014h) bit description bit symbol access value description 7 to 3 - 00000 not used 2 to 0 testpat_sel[2:0] r/w di gital test pattern select 000 off 001 mid scale 010 ? fs 011 +fs 100 toggle ?1111..1111?/?0000..0000? 101 custom test pattern 110 ?1010..1010.? 111 ?010..1010? table 27. test pattern register 2 (address 0015h) bit description bit symbol access value description 7 to 0 testpat_user[13:6] r/w 00000000 custom digital test pattern (bits 13 to 6)
ADC1415S_ser_3 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. preliminary data sheet rev. 03 ? 12 april 2010 33 of 39 nxp semiconductors ADC1415S series ADC1415S series; input buffer; cmos or lvds ddr digital outputs table 28. test pattern register 3 (address 0016h) bit description bit symbol access value description 7 to 2 testpat_user[5:0] r/w 000000 custom digital test pattern (bits 5 to 0) 1 to 0 - 00 not used table 29. fast otr register (address 0017h) bit description bit symbol access value description 7 to 4 - 0000 not used 3 fastotr r/w fast out-of-range (otr) detection 0 disabled 1 enabled 2 to 0 fastotr_det[2:0] r/w set fast otr detect level 000 ? 20.56 db 001 ? 16.12 db 010 ? 11.02 db 011 ? 7.82 db 100 ? 5.49 db 101 ? 3.66 db 110 ? 2.14 db 111 ? 0.86 db table 30. cmos output register (address 0020h) bit description bit symbol access value description 7 to 4 - 0000 not used 3 to 2 dav_drv[1:0] r/w drive strength for dav cmos output buffer 00 low 01 medium 10 high 11 very high 1 to 0 data_drv[1:0] r/w drive str ength for data cmos output buffer 00 low 01 medium 10 high 11 very high
ADC1415S_ser_3 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. preliminary data sheet rev. 03 ? 12 april 2010 34 of 39 nxp semiconductors ADC1415S series ADC1415S series; input buffer; cmos or lvds ddr digital outputs table 31. lvds ddr output register 1 (address 0021h) bit description bit symbol access value description 7 to 6 - 00 not used 5 davi_x2_en r/w double lvds current for dav lvds buffer 0 disabled 1 enabled 4 to 3 davi[1:0] r/w lvds current for dav lvds buffer 00 3.5 ma 01 4.5 ma 10 1.25 ma 11 2.5 ma 2 datai_x2_en r/w double lvds current for data lvds buffer 0 disabled 1 enabled 1 to 0 datai[1:0] r/w lvds current for data lvds buffer 00 3.5 ma 01 4.5 ma 10 1.25 ma 11 2.5 ma table 32. lvds ddr output register 2 (address 0022h) bit description bit symbol access value description 7 to 4 - 0000 not used 3 bit/byte_wise r/w ddr mode for lvds output 0 bit wise (even data bits output on dav rising edge / odd data bits output on dav falling edge) 1 byte wise (msb data bits output on dav rising edge / lsb data bits output on dav falling edge) 2 to 0 lvds_intter[2:0] r/w in ternal termination for lvds buffer (dav and data) 000 no internal termination 001 300 010 180 011 110 100 150 101 100 110 81 111 60
ADC1415S_ser_3 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. preliminary data sheet rev. 03 ? 12 april 2010 35 of 39 nxp semiconductors ADC1415S series ADC1415S series; input buffer; cmos or lvds ddr digital outputs 12. package outline fig 25. package outline sot618-6 (hvqfn40) references outline version european projection issue date iec jedec jeita sot618-6 - - - mo-220 sot618-6_po unit mm max nom min 1.00 0.85 0.80 0.05 0.02 0.00 0.30 0.21 0.18 0.2 6.1 6.0 5.9 6.1 6.0 5.9 0.5 0.1 0.05 a (1) dimensions note 1. plastic or metal protrusions of 0.075 mm maximum per side are not included. h vqfn40: plastic thermal enhanced very thin quad flat package; no leads; 4 0 terminals; body 6 x 6 x 0.85 mm sot618- 6 a 1 bcd (1) 0.1 y 1 d h 4.55 4.40 4.25 e (1) e h 4.55 4.40 4.25 ee 1 4.5 e 2 4.5 l 0.5 0.4 0.3 vw 0.05 y 0 2.5 5 mm scale terminal 1 index area terminal 1 index area b d a e b e 1 e a c b v c w 11 20 e 2 e 21 30 d h 31 40 e h l 1 10 c y c y 1 x c detail x a 1 a 1/2 e 1/2 e 09-02-23 09-03-04
ADC1415S_ser_3 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. preliminary data sheet rev. 03 ? 12 april 2010 36 of 39 nxp semiconductors ADC1415S series ADC1415S series; input buffer; cmos or lvds ddr digital outputs 13. revision history table 33. revision history document id release date data sheet status change notice supersedes ADC1415S_ser_3 20100412 preliminary data sheet ADC1415S065_080_105_125_2 modifications: ? figure 11 ? reference equivalent schematic ? has been updated. ADC1415S065_080_105_125_2 20090604 objective data sheet - ADC1415S065_080_105_125_1 ADC1415S065_080_105_125_1 20090528 objective data sheet - -
ADC1415S_ser_3 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. preliminary data sheet rev. 03 ? 12 april 2010 37 of 39 nxp semiconductors ADC1415S series ADC1415S series; input buffer; cmos or lvds ddr digital outputs 14. legal information 14.1 data sheet status [1] please consult the most recently issued document before initiating or completing a design. [2] the term ?short data sheet? is explained in section ?definitions?. [3] the product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple device s. the latest product status information is available on the internet at url http://www.nxp.com . 14.2 definitions draft ? the document is a draft versi on only. the content is still under internal review and subject to formal approval, which may result in modifications or additions. nxp semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall hav e no liability for the consequences of use of such information. short data sheet ? a short data sheet is an extract from a full data sheet with the same product type number(s) and title. a short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. for detailed and full information see the relevant full data sheet, which is available on request vi a the local nxp semiconductors sales office. in case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. product specification ? the information and data provided in a product data sheet shall define the specification of the product as agreed between nxp semiconductors and its customer , unless nxp semiconductors and customer have explicitly agreed otherwis e in writing. in no event however, shall an agreement be valid in which the nxp semiconductors product is deemed to offer functions and qualities beyond those described in the product data sheet. 14.3 disclaimers limited warranty and liability ? information in this document is believed to be accurate and reliable. however, nxp semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. in no event shall nxp semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interrupt ion, costs related to the removal or replacement of any products or rework charges) whether or not such damages are based on tort (including negligence), warranty, breach of contract or any other legal theory. notwithstanding any damages that customer might incur for any reason whatsoever, nxp semiconductors? aggregate and cumulative liability towards customer for the products described herein shall be limited in accordance with the terms and conditions of commercial sale of nxp semiconductors. right to make changes ? nxp semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. this document supersedes and replaces all information supplied prior to the publication hereof. suitability for use ? nxp semiconductors products are not designed, authorized or warranted to be suitable for use in life support, life-critical or safety-critical systems or equipment, nor in applications where failure or malfunction of an nxp semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. nxp semiconductors accepts no liability for inclusion and/or use of nxp semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer?s own risk. applications ? applications that are described herein for any of these products are for illustrative purpos es only. nxp semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. customers are responsible for the design and operation of their applications and products using nxp semiconductors products, and nxp semiconductors accepts no liability for any assistance with applications or customer product design. it is customer?s sole responsibility to determine whether the nxp semiconductors product is suitable and fit for the customer?s applications and products planned, as well as fo r the planned application and use of customer?s third party customer(s). customers should provide appropriate design and operating safeguards to minimize the risks associated with their applications and products. nxp semiconductors does not accept any liability related to any default, damage, costs or problem which is based on any weakness or default in the customer?s applications or products, or the application or use by customer?s third party customer(s). customer is responsible for doing all necessary testing for the customer?s applic ations and products using nxp semiconductors products in order to av oid a default of the applications and the products or of the application or use by customer?s third party customer(s). nxp does not accept any liability in this respect. limiting values ? stress above one or more limiting values (as defined in the absolute maximum ratings system of iec 60134) will cause permanent damage to the device. limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the recommended operating conditions section (if present) or the characteristics sections of this document is not warranted. constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device. terms and conditions of commercial sale ? nxp semiconductors products are sold subject to the gener al terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms , unless otherwise agreed in a valid written individual agreement. in case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply. nxp semiconductors hereby expressly objects to applying the customer?s general terms and conditions with regard to the purchase of nxp semiconducto rs products by customer. no offer to sell or license ? nothing in this document may be interpreted or construed as an offer to sell products t hat is open for acceptance or the grant, conveyance or implication of any lic ense under any copyrights, patents or other industrial or intellectual property rights. export control ? this document as well as the item(s) described herein may be subject to export control regulations. export might require a prior authorization from national authorities. document status [1] [2] product status [3] definition objective [short] data sheet development this document contains data from the objecti ve specification for product development. preliminary [short] data sheet qualification this document contains data from the preliminary specification. product [short] data sheet production this docu ment contains the product specification.
ADC1415S_ser_3 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. preliminary data sheet rev. 03 ? 12 april 2010 38 of 39 nxp semiconductors ADC1415S series ADC1415S series; input buffer; cmos or lvds ddr digital outputs non-automotive qualified products ? unless this data sheet expressly states that this specific nxp semicon ductors product is automotive qualified, the product is not suitable for automotive use. it is neither qualified nor tested in accordance with automotive testing or application requirements. nxp semiconductors accepts no liabili ty for inclusion and/or use of non-automotive qualified products in automotive equipment or applications. in the event that customer uses t he product for design-in and use in automotive applications to automotive s pecifications and standards, customer (a) shall use the product without nxp semiconductors? warranty of the product for such automotive applicat ions, use and specifications, and (b) whenever customer uses the product for automotive applications beyond nxp semiconductors? specifications such use shall be solely at customer?s own risk, and (c) customer fully indemnifies nxp semiconductors for any liability, damages or failed product claims resulting from customer design and use of the product for automotive app lications beyond nxp semiconductors? standard warranty and nxp semiconduct ors? product specifications. 14.4 trademarks notice: all referenced brands, produc t names, service names and trademarks are the property of their respective owners. 15. contact information for more information, please visit: http://www.nxp.com for sales office addresses, please send an email to: salesaddresses@nxp.com
nxp semiconductors ADC1415S series ADC1415S series; input buffer; cmos or lvds ddr digital outputs ? nxp b.v. 2010. all rights reserved. for more information, please visit: http://www.nxp.com for sales office addresses, please se nd an email to: salesaddresses@nxp.com date of release: 12 april 2010 document identifier: ADC1415S_ser_3 please be aware that important notices concerning this document and the product(s) described herein, have been included in section ?legal information?. 16. contents 1 general description . . . . . . . . . . . . . . . . . . . . . . 1 2 features and benefits . . . . . . . . . . . . . . . . . . . . 1 3 applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 4 ordering information . . . . . . . . . . . . . . . . . . . . . 2 5 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 3 6 pinning information . . . . . . . . . . . . . . . . . . . . . . 4 6.1 pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 6.2 pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4 7 limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 6 8 thermal characteristics . . . . . . . . . . . . . . . . . . 6 9 static characteristics. . . . . . . . . . . . . . . . . . . . . 7 10 dynamic characteristics . . . . . . . . . . . . . . . . . 10 10.1 dynamic characteristics . . . . . . . . . . . . . . . . . 10 10.2 clock and digital output timing . . . . . . . . . . . . 12 10.3 spi timings . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 11 application information. . . . . . . . . . . . . . . . . . 16 11.1 device control . . . . . . . . . . . . . . . . . . . . . . . . . 16 11.1.1 spi and pin control modes . . . . . . . . . . . . . . . 16 11.1.2 operating mode selection. . . . . . . . . . . . . . . . 16 11.1.3 selecting the output data standard . . . . . . . . . 16 11.1.4 selecting the output data format. . . . . . . . . . . 17 11.2 analog inputs . . . . . . . . . . . . . . . . . . . . . . . . . 17 11.2.1 input stage . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 11.2.2 transformer . . . . . . . . . . . . . . . . . . . . . . . . . . 18 11.3 system reference and power management . . 19 11.3.1 internal/external references . . . . . . . . . . . . . . 19 11.3.2 reference gain control . . . . . . . . . . . . . . . . . . 20 11.3.3 common-mode output voltage (v o(cm) ) . . . . . 20 11.3.4 biasing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 11.4 clock input . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 11.4.1 drive modes . . . . . . . . . . . . . . . . . . . . . . . . . 21 11.4.2 equivalent input circuit . . . . . . . . . . . . . . . . . . 22 11.4.3 duty cycle stabilizer . . . . . . . . . . . . . . . . . . . . 22 11.4.4 clock input divider . . . . . . . . . . . . . . . . . . . . . 22 11.5 digital outputs . . . . . . . . . . . . . . . . . . . . . . . . . 23 11.5.1 digital output buffers: cmos mode . . . . . . . . 23 11.5.2 digital output buffers: lvds ddr mode . . . . . 24 11.5.3 data valid (dav) output clock . . . . . . . . . . . . . 25 11.5.4 out-of-range (otr) . . . . . . . . . . . . . . . . . . . . 25 11.5.5 digital offset . . . . . . . . . . . . . . . . . . . . . . . . . . 25 11.5.6 test patterns . . . . . . . . . . . . . . . . . . . . . . . . . . 25 11.5.7 output codes versus input voltage . . . . . . . . . 26 11.6 serial peripheral interfac e (spi) . . . . . . . . . . . 26 11.6.1 register description . . . . . . . . . . . . . . . . . . . . 26 11.6.2 default modes at start-up . . . . . . . . . . . . . . . . 27 11.6.3 register allocation map . . . . . . . . . . . . . . . . . 29 12 package outline. . . . . . . . . . . . . . . . . . . . . . . . 35 13 revision history . . . . . . . . . . . . . . . . . . . . . . . 36 14 legal information . . . . . . . . . . . . . . . . . . . . . . 37 14.1 data sheet status . . . . . . . . . . . . . . . . . . . . . . 37 14.2 definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 14.3 disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . 37 14.4 trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . 38 15 contact information . . . . . . . . . . . . . . . . . . . . 38 16 contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

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